发明名称 MASTER METHOD OF MASTER SLICE LSI
摘要 PURPOSE:To make it possible to reduce the area in mounting memories, by arranging embedded basic cells exclusively for memories used under the wiring region between basic cells, using both the basic cells and the embedded basic cells when the memories are constituted, thereby mounting logic gates and memories at a high density. CONSTITUTION:In an LSI chip 1, basic cells 91, which can constitute random gates and memories are aligned in the direction of the X axis so as to form basic cell lines 4. The basic cell lines 4 are alternately arranged so as to hold each wiring region 93. Embedded basic cells 92, which can readily constitute memories, are aligned in the direction of the X axis under the wiring region 93, and embedded basic cell lines 90 is constituted. When the desired LSI is constituted by only the random gates, only the basic cells 91, which are arranged in the basic cell lines 4, are used and the embedded basic cells 92, which are arranged in the embedded basic cell lines 90, are not used. Then, the part over the cells 92 is used as a wiring region 93. When the desired LSI forms a logic area including memories, both cells of the basic cells 91 and the embedded basic cells 92, which are included in a memory region 94, are used and the memories are constituted.
申请公布号 JPS5972742(A) 申请公布日期 1984.04.24
申请号 JP19820182777 申请日期 1982.10.20
申请人 HITACHI SEISAKUSHO KK;HITACHI ENGINEERING KK 发明人 IKEDA MICHIHIRO;KUBOKI SHIGEO;NISHIO YOUJI;MASUDA IKUROU
分类号 H01L27/092;H01L21/82;H01L21/8238;H01L27/118 主分类号 H01L27/092
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