发明名称 Rahmen-Synchronisierungsanordnung
摘要 The decoder produces output containing a detectable signal component equal to one-half the frame repetition rate when an out of sync condition is present. A bandpass filter detects the signal component and produces a pulse which is inserted into the bit clock from which the frame clock is derived for operating the decoder. The frame clock is shifted one bit each frame until a sync condition is achieved and the signal component disappears. A feedback circuit inhibiting the filter output is provided to prevent for a given time interval generating a succession of additional pulses after the first extra pulse is inserted into the bit clock.
申请公布号 DE1946109(A1) 申请公布日期 1970.03.26
申请号 DE19691946109 申请日期 1969.09.11
申请人 INTERNATIONAL STANDARD ELECTRIC CORP. 发明人 HOOD MCNEILLY,JOSEPH;BARTON,PAUL
分类号 H04J3/06;H04L7/027;H04L7/08 主分类号 H04J3/06
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