| 摘要 |
PURPOSE:To attain the sufficient use of the titled line even to a digital automatic equalizer having a fast symbol clock by providing two sets of delay line circuits consisting of an RAM and inputting alternately a new data at each symbol clock to each circuit. CONSTITUTION:Switching signals SW1, SW2 fetch input data I10, I20, inputted at each symbol clock in a period twice the symbol clock to a delay line to which eadh switch belongs via switching gates 21, 21'. The fetched input data is outputted for two symbol clock's share with a delay of the period's share of one symbol clock from output buffer registers 24, 24' via RAMs 23, 23' by switching the SW1, SW2. In case of Figs. A, C, the output of an OUTBout 1 is inputted to an operating device 26 via a switching gate 27 and inputted to an operating device 26' in case of Fig. B. The output of an OUTBout 2 is inputted to the operating device 26' in case of Figs. A, C, and inputted to the operating device 26 in case of Fig. B. Since the operating speed of the two delay lines is a half of the conventional line speed, the phase margin is twice as large. |
