| 摘要 |
PURPOSE:To reduce the number of output terminals of a memory circuit, by latching information read out from respective memory circuit block and transmitting them successively to an output terminal in time division. CONSTITUTION:Since a period td from a time t1 of a change of the address signal to a time t3 of generation of a clock signal is set to a value longer than an access time tAC and is shorter than the holding time of the address signal, latch circuits L1-L4 latch output data D1-D4 during a hold time tCYC of the address signal. The second clock signal phi2 having four clock pulses P1-P4 during the holding time tCYC of the address signal is applied to a multiplexer MPX, and latch data LD1 of the latch circuit L1 is outputted to an output terminal DOUT by the clock pulse P1, and hereafter, data LD2, LD3, and LD4 are outputted to the output terminal DOUT successively. Thus, four-bit output data is outputted from the single output terminal DOUT. |
