发明名称 PACKET SWITCHING CONTROL SYSTEM
摘要 PURPOSE:To attain a high speed packet switching, by using the right of usage being the guarantee of receiving of a packet for an addressed resource of opposite party and the right of usage of a common data bus as a token, so as to transmit/receive the data on a control bus provided as a loop. CONSTITUTION:When there exists a packet to be transferred in a transmission buffer memory of the own channel, a corresponding RVi is set to busy state (RVi=1) and the occupancy of the right of usage is declared, by monitoring a control bus 42 with an I/D circuit and a busy/idle detecting circuit and waiting for an RVi signal having a number coincident with the address of the packet, i.e., the idle state (not in use RVi=0) of the opposed receiving buffer memory. The packet in the transmission buffer memory is transferred through the common data bus 41. A DB of the control bus signal is reset to the idle state (DB= 0) by detecting the end of packet transfer and the right of usage of common data bus is given up.
申请公布号 JPS5958936(A) 申请公布日期 1984.04.04
申请号 JP19820168277 申请日期 1982.09.29
申请人 FUJITSU KK 发明人 SATOU KEIJI;NAKAMURA YOSHIHIRO;FUKATSU SADAO
分类号 H04L12/56 主分类号 H04L12/56
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