| 摘要 |
A high-speed, high-resolution testing circuit for both analog and digital circuit packs is described. The testing circuit, which employs data compression techniques, comprises a shift register (22) having an overall length selectively variable under program control, and an arrangement (18) for combining incoming data signals with feedback signals out of predetermined stages of the shift register. The positions of the feedback taps of the variable length shift register are selectively variable under program control (24,26).
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