| 摘要 |
An address input buffer for a cross-coupled latch of the type including two switching transistors with output nodes "a" and "b". The address input buffer circuit structure includes a first depletion device having its source electrode connected to latch node "b" and the address input voltage connected to its gate, and a second depletion device having its source electrode connected to latch node "a" and to its gate so that the voltage differential across the latch is a function of the variable current difference between the two depletion devices because the gate to source voltage of one depletion device is constant and the gate to source voltage of the other depletion device is variable in accordance with the level of the address input voltage. Thus, the address input voltage is not compared to a fixed reference voltage, and no capacitive boosting of a reference and address voltage is necessary to turn on the latch. Embodiments of the address input buffer circuit for both static and dynamic random access memory applications are also disclosed.
|
