| 摘要 |
A digital adder circuit for binary-coded-decimal operation, comprising a set of multiplexers (11) which are conditioned with a pattern of input bits causing them to form an intermediate result (IR) equal to the sum of the two operands (A0-A3, B0-B3) plus a correction value of six. The intermediate result is adjusted by subtracting the correction value if the intermediate result is less than sixteen. The circuit is also operable in a pure binary mode, or can be made to perform various logical operations.
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