| 摘要 |
PURPOSE:To attain the unified allotment of addresses, by providing data memory regions for parallel processing with addresses to all controllers and allotting absolute addresses to those memory regions as transmission data regions and at the same time transferring those absolute addresses to a receiving region. CONSTITUTION:A programmable controller 11 is connected in parallel to other plural controllers by a transmission line 6, and the line 6 is connected to an arithmetic part 11-1 of the controller 11 through a transmission/reception circuit 7, a transmission/reception control circuit 8, a transmission/reception data buffer memory 9 and a parallel processing data memory 10. All controllers connected in parallel to each other have parallel processing data memories 10 of (a)-(e) which share an address. These controllers are divided into (a)-(e) in response to the number of stations and data. At a station #0 the region (a) is allotted as a transmission region to other stations with regions (b)-(e) allotted as the reception regions to other stations respectively. In such a way, just an address exists to the same signal. |
