| 摘要 |
<p>An insulated-gate field-effect transistor which may be of a vertical power D-MOS type comprises surface-adjacent source and emitter regions (10 and 15) surrounded in a semiconductor body (1) by a surface-adjacent second region (20) of opposite conductivity type. A third region (30) adjoins the second region and has a lower conductivity-type determining doping concentration. At least a part of these second and third regions is located in a main current path from the source region (10) to a drain (31) of the transistor, and an insulated gate (4) which may be of metal-silicide capacitively controls a conductive channel at least in this part (21) of the second region (20). The emitter region (15) is located at a side of the source region (10) remote from the channel part (21) and is separated therefrom by an intermediate part (22) of the second region (20). The source region is electrically connected to this intermediate part (22), for example by a short-circuiting metal-silicide layer (8). A resistive current path (25) in the second region (20) is present below the emitter region (10) and extends from this intermediate part (22) to a further part (23) of the second region (20) which is electrically connected to the emitter region (15), for example by a short-circuiting metal-silicide layer (9). A source electrode (2) is electrically connected to this further part (23) so as to be electrically connected via the resistive current path (25) to the source region (10). The emitter region (15) serves to modulate the conductivity of the third region (30) and so reduce the drain series resistance of the transistor, by charge-carrier injection from the intermediate part (22) when the source-drain current along the resistive current path (25) is sufficient to forward-bias the intermediate part (22) with respect to the third region (30).</p> |
