| 摘要 |
PURPOSE:To improve the reliability of a system and its function, by storing an input serial bit data in the shift pulse period, using a gate circuit output outputting the content as a clear signal, and generating a sampling pulse so as to prevent mis-receiving even when impulsive noise exists. CONSTITUTION:A positive noise pulse is fetched in shift registers 1-3, and since an FF7 is set, an output of an AND gate 5 is inhibited at a signal line 14, and no clear signal 12 of a sampling counter 6 is outputted. The FF7 is reset via a signal line 15 at the leading when a value 1 of serial bit data is received. The FF7 stores the correct trailing of the serial bit data until the detection of trailing of the next estimated bit data and inhibits an output of the clear signal of the counter 6, then the counter 6 is not cleared erroneously by the trailing edge of noise pulse. |
