| 摘要 |
<p>A large scale integrated semiconductor device manufactured by using master-slice technology comprising a plurality of unit cells (11, 12, 13, 14, ...) external connections made between the unit cells, interconnections within each unit cell which connect the circuit elements of that cell to each other, and bypass connections within unused areas of the unit cells for connecting other neighbouring unit cells together. The bypass connections are arranged in accordance with an imaginary grid which is of a different type and is displaced from another imaginary grid which defines the position of the unit cells and their external connections. (External- and interconnections are shown right-hatched, bypass connections cross-hatched). Less space is required for external connections by using space within unit cells which would otherwise be wasted for the bypass connections between neighbouring unit cells. Several unit cells can be joined together to share external terminals.</p> |
