发明名称 Multilevel metallization process for integrated circuits
摘要 A multilevel metallization process which allows fabrication of several types of high density MOS and bipolar integrated circuits. The process uses a pad located under the inter-layer contact opening. The material of the pad is poly-silicon (doped or undoped), a refractory metal, or a refractory metal silicide which is not capable of being attacked during chemical etching of the metallization layers. If poly-silicon is used, it is either doped during its deposition or during contact doping, or it is automatically silicided during ohmic and Schottky contact formations.
申请公布号 US4436582(A) 申请公布日期 1984.03.13
申请号 US19800201109 申请日期 1980.10.28
申请人 SAXENA, ARJUN N. 发明人 SAXENA, ARJUN N.
分类号 H01L21/768;H01L23/532;(IPC1-7):C23F1/02 主分类号 H01L21/768
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