| 摘要 |
A clock circuit for clocking video image signals in a raster scanner. The clock circuit includes an inverting gate enabled during scanning with gate output feedback to gate input through an adjustable time delay, the delay inherent in the gate being summed with the delay of the adjustable time delay to provide gate switching and clock output. A register compares clock scan line frequency with preselected scan line resolution and a phase comparator compares scan duration with register output to control clock frequency. |
