| 摘要 |
PURPOSE:To facilitate the clock signal reproduction by adding an input clock signal and its inverted phase delay signal, integrating the result to detect the fundamental frequency signal of the jitter thereby eliminating the fundamental frequency signal of the jitter from the inputted clock signal. CONSTITUTION:The 1st clock signal inputted from a clock signal input terminal 1 and the 2nd clock signal inputted via the inverted phase delay circuit 2 are added by the 1st adder circuit 3. The output of the circuit 3 is intergrated by an integration circuit 5 via a low pass filter 4 and the frequency signal being the major component of jitter is outputted. The phase of the jitter signal is fixed by a PLL circuit 6 and the result is inputted to the 2nd addition circuit 10 via an amplifier 8. On the other hand, the clock signal inputted from the terminal 1 is subject to phase adjustment by a phase adjusting circuit 9 so that its jitter component is made opposite in phase to that of the output of the amplifier 8 gain-controlled by the peak of the jitter signal via a peak detection circuit 7, the result is inputted to the circuit 10, from which the clock signals whose jitter component is eliminated is outputted. |
