| 摘要 |
A processor, for providing a double line-rate video signal comprising alternating received lines and interpolated lines, comprises three memories (32,34,36) each having capacity to store one video line. As each incoming video signal line is stored in one of the three memories, the remaining two are read at double the write clock rate. An output circuit (54,60-70) provides a processed video output signal by interleaving a non-interpolated time compressed line of video, obtained from one of the two memories being read, with a time-compressed line of video obtained by interpolation (by averaging circuitry such as 60,66) from both of the two memories being read. The write-one read-two memory organization enables concurrent interpolation and speed-up of the video signal thereby minimizing potential clock timing problems inherent in progressive scan systems of the type where interpolation is provided separately either before or after video speed-up. |
