| 摘要 |
A converter for converting a binary digital code into an analog representation. The converter includes a timing system which is operated by a clock signal to produce a synchronized timing pulse. The digital information is fed into a holding register, and such is gated through a plurality of gates that feeds the complement of the digital code into a counter. The relative duration of the output signal of the last state of the counter in a logic "one" state corresponds to the weight of the digital code being fed into the holding register.
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