| 摘要 |
PURPOSE:To eliminate a latency time and to increase the effect of a memory sharing type multiprocessor, by allowing access to a shared memory preferentially for urgent processing. CONSTITUTION:A CPU21 is given priority to another CPU22, among two CPUs 21, 22. If the shared memory 29 is under use by the CPU22 when the CPU21 sends a request for access to the shared memory 29, a bus changeover switch control part 23 sends a queuing request to the CPU22 and this CPU stops. Consequently, the shared memory 29 is connected to the CPU21 and made accessible. When the CPU21 informs the switch control part 23 that the access is completed, the queuing request to the CPU is reset and the CPU22 restarts the interrupted access to the shared memory 29. |
