| 摘要 |
PURPOSE:To obtain a memory cell which can electrically erase information with low voltage by controlling the width of a deletion layer which expands from a drain region by a voltage applied to a drain electrode, and controlling the electric connection or disconnection except the source and drain regions of a semiconductor layer with the drain electrode. CONSTITUTION:A semiconductor region 11 has a structure which is contacted with a drain electrode 23 similarly to a drain region 13. When V2=VDD=5V, V1=0 are set, where V1 is a source voltage, V2 is a drain voltage and VDD is the drain operating voltage at the read-out time, a depletion layer 20 expands to reach a sapphire substrate 16, the region 11 is isolated, becoming in an electrically floated state. Information can be erased when the drain voltage V2 is set to V2=V2, because the layer 20 is contracted so that the region 11 is connected to the drain electrode 23 with the result that negative charge is erased. When V2=5V, V1=0V are set since this state is information ''0'', the layer 20 expands, the region 11 becomes in a floated state, a current flows between the drain and the source when a read-out voltage 6V is applied to the gate, and the current is detected, thereby reading out the information ''0''. |
