| 摘要 |
PURPOSE:To construct a high speed logic while holding a high integration by enhancing power consumption and accelerating a speed only in a buffer of specific position in a chip to reduce the power consumption of the entire chip. CONSTITUTION:A gate array semiconductor has twice or more power consumption as large as a normal output buffer except a normal output buffer and has output buffers 3 which can respond to a frequency of 100MHz or higher at symmetrical positions in the chip. Since the output buffer 3 exclusive for a high speed does not need a bidirectionality in use, it is used exclusively for output. 4 output buffers exclusive for a high speed are disposed symmetrically at the centers of the right and left sides, and buffers exclusive for inputs are disposed at upper and lower sides to improve the integration of the chip. |
