| 摘要 |
PURPOSE:To execute an arithmetic at a high speed even in case of using an arithmetic element whose arithmetic speed per bit is low, by obtaining an adder by which two series data trains are added successively from the maximum bit and the arithmetic is ended before the time slot of the minimum bit. CONSTITUTION:Each input terminal 25, 26 of data trains A, B to be added is connected to an AND gate 27 and an exclusive OR gate 28, respectively, and an output of the AND gate 27 and an output of the exclusive OR gate 28 are used as a load signal of a D-register 23 and a data signal of the D-register 23, respectively. Also, the output of the gate 28 is inverted by an inverting gate 29 and is used as a load signal of a T-register 22, too. Also, the output of an AND gate 27 and an output of the inverting gate 29 are applied to an NOR gate 30, and an output of this gate becomes a clear signal of a load enable control register 24. |
