| 摘要 |
A binary-coded-decimal to binary converter employs a selection network to which the binary coded decimal digits are applied, the digits being selected in pairs of increasing order of decimal denominational significance to be passed to the address lines of a pair of memory elements, the locations of which contain the binary terms equivalent to the decimal digits from which the particular location address is derived. In order to increase the effective utilization of the memory elements, the binary code components specifying at least one of the decimal digits are manipulated by the selection network, for example by conversion to complementary form, before being applied to the address lines. The notional capacity of the locations in terms of the number of binary denominations specifiable may be increased by separately generating bits of higher denominational significance, and this separate generation may take the form of a logic gating operation applied either to generate a binary term directly or to re-allocate the denominational significances of bit positions within a location.
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