| 摘要 |
PURPOSE:To easily detect an address of a cell from the external by providing an output circuit which uses one external terminal other than the address terminal to output the detection signal of a detecting circuit to the external and a mode switching circuit which validates the output circuit only when a test signal is applied to another external terminal. CONSTITUTION:At the test time, a voltage higher than that for normal operation is applied to a terminal 6 to set the output of a mode switching circuit 3 using a high voltage detecting buffer BUF0 to the high level. Though the output of a buffer BUF1 of the normal operation mode is set to the high level also, an output the inverse of CE of an AND gate AND10 goes to the low level because the output of an inverter INV1 goes to the low level. Simultaneously, an output the inverse of OE of an AND gate AND11 goes to the low level, and therefore, the memory is set to the read mode. In case of S=1 (presence of error), the output of an inverter INV3 goes to the low level and is outputted to the external through a terminal 7 to indicate the presence of error; but in case of S=0 (absence of error), the output of an inverter INV2 goes to the high level. Thus, the address of an error bit is easily detected from the external.
|
