| 摘要 |
PURPOSE:To realize a ternary level clock generating circuit with extremely less power consumption, by generating a ternary level clock which operates in an integrated circuit using a single power source and has the polarity opposite to a source voltage. CONSTITUTION:The source of a p channel MOSFETQ1 is connected to the 1st power source line with a voltage VDD, the drain is connected to an output terminal N1, and the gate is connected to a signal line for a clock phi2 for driving the MOSFETQ1. Then, the drain of an n channel MOSFETQ2 is connected to an output terminal N1 and the source is connected to the 2nd power source line with a voltage GND. The output terminal N1 is connected to a signal line for a clock phi1 through a coupling capacitor, a node N2 is connected to the signal line for the clock phi1 through the coupling capacitor C1, and a node N2 is connected to an output terminal N2 through a coupling capacitor C2. Further, the drain of an n channel MOSFETQ3 is connected to the node N2, the source is connected to the signal line for the clock phi2 for driving the MOSFETQ2, and the gate is connected to a signal line for a clock phi4. |
