| 摘要 |
<p>Digital computer with a programmable memory organization arranged in a bit sliced fashion. The address inputs of the N memories (10-1 to 10-N) of the memory structure are operands and opcodes. The N memories (10-1 to 10-N) provide transformations of the operands, which transformations are defined by the opcodes. …<??>The outputs of the memories are applied to the address register (12) of a further control memory (15) that stores control words. …<??>One portion of the control words retrieved from memory (15) is coupled to the opcode address input of each of the N memories (10-1 to 10-N) …<??>The operand address inputs of the N memories are derived from registers (12, 14, R1 to RN). …<??>A similar programmable structure can be employed in the data section of the computer.</p> |
