| 摘要 |
PURPOSE:To contrive to prevent the titled device from generation of a parasitic MOS without reducing the degree of integration of IC's by a method wherein an electrode is provided on the whole surface holding at high electric potential on a group of wirings interposing a second insulating film between them, and a high concentration diffusion layer the same conductive type with a substrate is provided as the channel stopper between diffusion layers containing the part directly under the wirings to cross the diffusion layers thereof. CONSTITUTION:When the Al wirings 21 exist on the p type diffusion layers of two pieces crossing them, the high electric potential Al electrode 16 is formed on the whole surface interposing the insulating film 15 between them, and the n<+> type diffusion layer 22 is provided partially as the channel stopper between the two diffusion layers at the part containing the directly under part of the Al wiring 21. Accordingly, unstably movable ions on the surface of the semiconductor are fixed according to bias to the high electric potential electrode 16 to prevent the semiconductor from formation of an inversion layer on the surface, and by forming the high electric potential electrode 16 on the whole surface, an optional countermeasure to cope with generation of a parasitic MOS according to migration of negative electric charge is established, the influence of the parasitic MOS generated under the wiring electrodes 21 can be obstructed effectively by the partial channel stopper 22, and because formation of a channel stopper to surround the whole of the p type diffusion layers is made to be unnecessary, to increase chip size is made to be needless. |
