| 摘要 |
PURPOSE:To decrease the number of elements for a counter circuit which is needed for detection of a tuning shift from a positive tuning point of an intermediate frequency, by using a D flip-flop to count the tuning shift from the positive tuning point. CONSTITUTION:When an automatic channel selection start signal SF is generated, a clock pulse RCTR is applied to an up-down counter 9. Then the channel is changed to N+1 from N, and a counter circuit 2 is reset. Thus a time base signal TB is set at L, and the circuit 2 starts counting. When the count value reaches 9,000 within a fixed period of 100m sec the output of an AND gate 3 is set at H. While the circuit 2 starts counting the detuning frequency of a DFF1 if the count value does not reach 9,000. Therefore, the output G1 of an AND gate 5 is also set at H, and the output SFQ of a JKFF6 is inverted to H. As a result, a frequency dividing circuit 14 is reset and no RCTR is applied to the counter 9. Then the automatic channel selection is discontinued. |
