发明名称 PHASE LOCKED LOOP
摘要 PURPOSE:To form an analog phase locked loop by constituting the loop so as to be applied to an MOS integrated circuit and require no complex phase comparator. CONSTITUTION:Since outputs with phases reversed each other are outputted from output terminals 7, 8 of a voltage control oscillating circuit 6, one status of the whole circuit is that an MOS field effect transistor (MOSFET) 1 is connected and an MOSFET 2 is disconnected and the other status is the reverse status. In the 1st status, an input signal from a terminal 9 is applied to a terminal 11 of an operational amplifier circuit 4 to charge/discharge a capacitor 5. The change of potential on an output terminal 13 causes the oscillation frequency of the voltage control oscillating circuit 6 to change. In the 2nd status, the oscillation frequency is not changed. When the phase of an input signal is shifted by 90 deg. or -90 deg. from that of an output from the circuit 6 through the terminal 7, the average change of the charge of the capacitor 5 is zero and the circuit is kept at the steady status. Under said status, the frequency of the input signal coincides with the oscillation frequency of the circuit 6 and the circuit 6 operates as a phase locked loop.
申请公布号 JPS5913428(A) 申请公布日期 1984.01.24
申请号 JP19820122722 申请日期 1982.07.14
申请人 NIPPON DENKI KK 发明人 SUGIMOTO MASUNORI
分类号 H03L7/08;H03L7/085 主分类号 H03L7/08
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