| 摘要 |
<p>An efficient way to implement a binary adder on a large scale integrated (LSI) chip is disclosed. The logic path for both the sum and carry functions have been totally integrated and redundant input logic has been eliminated through the full utilization of MOS multiplexers (210-213). The result is a circuit with fewer transistors and a more compact and convenient layout over former techniques for any given length adder.</p> |
