发明名称 INPUT AND OUTPUT CONTROLLER
摘要 PURPOSE:To reduce the deviation of data transfer between channels, by providing plural transfer request signals between a data buffer and a main storage provided to each channel and generating a transfer request signal of higher priority as the transfer data quantity increases. CONSTITUTION:An input/output controller consists of a common part 10 and plural channel parts 30. When data is transferred to a peripheral controller 5 from a main storage 2, a transfer request signal 35 is delivered to a common control part 12 from a data transfer control part 34. At the part 34 a high or low priority signal is sent to the part 12 by switching and in response to the number of words to give access to the storage 2 for the data stored in a data buffer 32. The part 12 selects a channel part of the highest priority among the transfer request signals given from the channel parts 30. Then the data is read out of the storage 2 to a data register 13 with a main storage address related to the above-mentioned channel part. An access end signal 36 is sent to the channel part 30 as a reply. The channel part 30 fetches the readout data out of the register 13 to a writing register 31 and then stores it into the buffer 32.
申请公布号 JPS598041(A) 申请公布日期 1984.01.17
申请号 JP19820117329 申请日期 1982.07.05
申请人 NIPPON DENKI KK 发明人 SAKAMOTO AKIO
分类号 G06F12/08;G06F13/18;G06F13/362 主分类号 G06F12/08
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