| 摘要 |
<p>PURPOSE:To simplify a circuit without using a redundant logical element, by processing the first and the second operands and a carry input signal by the first and the second logical circuits, and also generating a carry signal through a selective gate circuit. CONSTITUTION:Multiplexers 210-213 provide a single ripple path to both of sum signals D0-D3 and a carry signal Cout. Therefore, a four bit adder is constituted of five multiplexers 210-214. Also, operands B0-B3 are used directly as inputs G0-G3 to the multiplexers 210-213. Also, a logical function of an AND gate is realized by utilizing an operation of a two-to-one multiplexer used for executing the sum and the carry function.</p> |
