| 摘要 |
PURPOSE:To make it possible to perform high speed operation, by forming gate electrodes and their wirings by a common high concentration polycrystal silicon layer, using the layer as a wiring between both cells, thereby reducing the wiring resistance especially at a wiring channel part. CONSTITUTION:Each gate electrode of both MISFETs 1 and 2 is formed by a common poly Si layer 15 with high concentration (e.g. 10<14>-10<15>/cm<3>). Said poly Si itself is extended as a wiring 5 and used for connecting opposing cell regions. When CMOS is manufactured (especially in a 3mum process), phosphorus treatment is performed on the entire surface after the poly Si for the gate electrodes is deposited. As this time, the entire poly Si layer is made to have high impurity concentration (an N electrode). Therfore, when P type impurities for forming source and drain regions of a P channel MISFET, e.g. of boron, are implanted at the next process, N type conductivity is held at high concentration in the poly Si gate electrode of said MOSFET. |
