| 摘要 |
PURPOSE:To prevent the input level margin from being decreased even if output circuits are switched at the same time, by making the on-resistance of a logical gate outputting signal, to an output circuit among logical gates forming an internal circuit larger than the on-resistance of other logical gates. CONSTITUTION:The output circuits 204, 205 and 206 are output ciruits possible for switching from ''1'' to ''0'' level at the same time. The output circuits switched simultaneously are driven by 4-input NORs 400, 401 and 402. When inputs 403, 404, 405 of the 4-input NOR are changed from ''1'' to ''0'' level in this way, PMOSs 406, 407, 408 are turned on, a current flows from a Vcc power supply and an input potential of the output circuits 204, 205, 206 is increased. the 4-input NORs 400, 401, 402 have a large ON-resistance, since 4-PMOS is arranged in series. Thus, the leading edge of the input signal to the output circuits 204, 205, 206 lags, allowing to suppress the floating of a GND potential. |
