发明名称
摘要 PURPOSE:The erading and writing is carried out by 1 bit for serial data, and the memory capable of reading and writing of parallel data is also equipped. Through the alternate switching of the above actions, the serial-parallel conversion is performed for the data. In this way, the serial-parallel conversion can be performed with minimized register number.
申请公布号 JPS5858875(B2) 申请公布日期 1983.12.27
申请号 JP19750131646 申请日期 1975.10.31
申请人 FUJITSU KK;NIPPON DENSHIN DENWA KOSHA 发明人 NAITO SHUNICHI;KOJIMA TAKUTO;SATO HIROAKI;KUBOYAMA YOSHIO
分类号 G06F3/06;G06F13/00;H04Q11/04 主分类号 G06F3/06
代理机构 代理人
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