发明名称 ABSOLUTE VALUE CIRCUIT
摘要 PURPOSE:To obtain an absolute value circuit with high preciseness suitable for being susceptible to IC formation, by simple circuit constitution without using an operation amplifier. CONSTITUTION:T1 and T2 are input erminals between which an alternating input signal is applied, T3 is an outut terminal, Q1-Q4 are input transistors connected to T1 and T2, Q5-Q7 are transistors constituting a PNP current mirror CM1, Q8 and Q9 constitute CM2, Q10-Q12 constitute CM3, Q13 and Q14 constitute CM4 and A15 and Q16 are output transistors. Because formula V1>V2 (Vi>0) is formed at the point of time t1-t2, Q3 is cut off and I3 comes to zero. In addition I1 and I4 are set so as to become equal and, when XY is set to 2, formula I4=I1=Vi/Rl=I8/2 is formed and a current proportional to an input signal is supplied to Q9. Similarily, because formula Vi<0 is formed at the point of time t2- t3, Q1 is cut off while formula I2=I3=Vi/R2=I14/2 is formed and a current proportional to the input signal Vi is supplied to Q13. Because Q15 and Q16 are connected to each bases of Q9 and Q13, I15 and I16 are made proportional to Vi and potential of T3 comes to a curve (b) shown by the drawing.
申请公布号 JPS58225358(A) 申请公布日期 1983.12.27
申请号 JP19820110107 申请日期 1982.06.25
申请人 MITSUBISHI DENKI KK 发明人 SATO HARUNORI;SAKANO RIYUUICHI
分类号 G01R19/22;G06G7/25;H02M7/12;H02M7/21 主分类号 G01R19/22
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