发明名称 CIRCUIT FOR GENERATING DEMODULATING CLOCK SIGNAL
摘要 PURPOSE:To generate demodulating clocks easily and precisely even if the number of revolutions of a motor is disturbed by varying inputs to a voltage controlling oscillator generating the demodulating clocks in accordance with phase comparison with synchronizing pulses with data signals. CONSTITUTION:Monostable multivibrators 8, 9 in a demodulating clock signal generating circuit 7 are triggered by the leading and trailing edges of a reproducing data pulse from a disc or the like and then NAND gates 19, 21 in a phase comparing circuit 13 to which a self-oscillation output from the voltage controlling oscillator 12 and a self-oscillation output through an inverter 20 are applied is controlled. The charging and discharging time of a capacitor C in an LPF 14 is controlled through FETs 22, 23 in accordance with the phase difference between a data pulse and an oscillation pulse from the oscillator 12 and the feedback of the oscillator 12 is controlled through a control circuit 18 to generate demodulating clocks. When the revolution of a motor is sharply disturbed at the starting time or the like, a switch 17 in the circuit 18 is changed over by a relay 24, a feedback input is expanded and the circuit 12 is controlled with high sensitivity. Thus the demodulating clocks can be generated easily and precisely even if the revolution of the motor is disturbed.
申请公布号 JPS58224419(A) 申请公布日期 1983.12.26
申请号 JP19820108934 申请日期 1982.06.23
申请人 SANYO DENKI KK;TOTSUTORI SANYOU DENKI KK 发明人 WASHIMI IKUAKI
分类号 G11B20/14 主分类号 G11B20/14
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