| 摘要 |
PURPOSE:To minimize errors in reproduced data and to improve the reliability of a titled device, by constituting a data detecting method which hardly produces errors, and a BI-PHASE decoding system. CONSTITUTION:Among reproduced analog signals (p) inputted into an input terminal 15, those having a >=OV comparing level become digital signals (s) of ''1'' and those having a <=OV comparing level becomes digital signals (s) of ''0'' by a binary comparator, and, on the other hand, a digital signal (r) for extracting clocks is obtained by a differentiator and the binary comparator. Then, the signal (s) is latched by a reproducing clock (v) and only the clock bit of FD signals is fetched out (w). In this case, only when ''11'' and ''00'' patterns are generated in the clock bit by the algorithm of an FD modulating system, the data bit between bits is ''1''. Therefore, when the exclusive ''OR'' of the signals (s) and (w) is found and this signal (x) is latched by the reproducing clock (v), an FD decode signal (y) is obtained. |
