发明名称 PULSE WIDTH MODULATION CIRCUIT
摘要 PURPOSE:To enable the circuit to act surely by simple structure by a method wherein circuits of N-1 bits are used as a gradient counter circuit and as a comparator circuit. CONSTITUTION:Frequency of a reference clock signal supplied to a clock terminal 135 is divided by a 1/2 frequency divider circuit 154, and is counted by the gradient counter 152 of N-1 bits. The counted value of the reference clock signal by the counter is held in a latch circuit 136. The output count value from the gradient counter circuit 152 and the counted value of N-1 bits held in the latch circuit 136 and removed with the lowermost level bit are compared by a comparator circuit 153. A control circuit consisting of D-FF's 156, 157, an AND circuit 155 and an OR circuit 158 discriminates whether the held value in the latch circuit 136 is the even number or the odd number according to the lowermost level bit of the latch circuit 136, and output of the comparison result as it is or delayed by the amount of 1 clock of the reference signal is outputted corresponding to the discrimination result thereof and the comparison result of the comparator circuit 153.
申请公布号 JPS58218883(A) 申请公布日期 1983.12.20
申请号 JP19820102821 申请日期 1982.06.15
申请人 TOKYO SHIBAURA DENKI KK 发明人 NISHIKAWA AKINARI;KOJIMA TADASHI;NANUN MASAHIDE
分类号 H03M1/82;G11B19/24;G11B19/28;H02P29/00;H03K7/08 主分类号 H03M1/82
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