| 摘要 |
PURPOSE:To reduce the area occupied by gate and to control gate length with a high accuracy by forming a gate at the stepped area which is vertical or almost vertical to the surface of substrate. CONSTITUTION:A silicon oxide film 2 is formed on a silicon semiconductor substrate 1 and a silicon nitride film 3 is formed thereon. The nitride film 3 and nitride film 4 are selectively removed and a groove 4 having vertical or almost vertical stepped portion 4a is formed. Next, the exposed surface is thermally oxidized and a oxide film 5 is formed. Thereafter, an oxide film 5 is removed and a gate oxide film 5 is formed. In this case, a nitride film 3 is extruded toward inside from the edge of groove 4. Next, a polycrystalline silicon film 7 is formed on the entire part of exposed surface. Thereafter, the polycrystalline silicon film 7 is left only at the vertical stepped portion by the anisotropic etching and a gate 8 is formed by self-matching. Next, a gate oxide film 8 other than the nitride film 3, oxide film 2 and gate 8 is removed and the source region 9 is formed in the periphery of groove 4, while the drain region 10 at the bottom part. Thereafter, an oxide film 11 is formed, and moreover a gate electrode 12, source electrode 13 and drain electrode 14 are formed thereon. Thereby, a gate length can be controlled accurately by controlling the etching time. |
