发明名称 ASYNCHRONOUS DOWN-COUNTER
摘要 PURPOSE:To obtain a down-counter which can be used with the decimal system with no malfunction, by using a pulse generating circuit which sets the contents of the flip-flop circuits connected longitudinally in plural steps to a prescribed code and has its output that is extracted with a 1-clock time delay compared with the output of a detecting circuit. CONSTITUTION:An NAND gate 4 which functions as a detecting circuit detects a state in which no hazard is generated, i.e., a state of ''0'' which is set before all flip-flop circuits 3a-3d are set at ''1''. This detected state is sotred in a latch circuit 5 which functions as a storage circuit. All flip-flops are changed to ''1'' from ''0'' with the next clock. This time point is obtained by an AND of either none of outputs of circuits 3a-3d (3a used in the diagram) and the output of the circuit 5. This output actuates a monostable multivibrator which functions as a pulse generator 7. Then the circuits 3a and 3d are set at ''1''; while the circuits 3b, 3c and 5 are set at ''0''. Thus a decimal down-counter is started.
申请公布号 JPS58206236(A) 申请公布日期 1983.12.01
申请号 JP19820088995 申请日期 1982.05.26
申请人 NIPPON DENKI KK 发明人 NAKADA HIDEO
分类号 H03K23/58;H03K23/00;H03K23/62;H03K23/66;H03K23/72 主分类号 H03K23/58
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