发明名称 MEMORY ADDRESS ASSIGNING DEVICE
摘要 PURPOSE:To make an address assignment of a memory block in block unit easy, by inputting a memory block selection signal out of a decoder, and providing with a switching means which switches and inputs the selection signal to an optional block out of plural memory blocks. CONSTITUTION:According to the operation of a switch operation part SWC, an output terminal 3 of a decoder DEC is connected to a selection signal input terminal CE of a memory block M1, and an output terminal 4 of the decoder DEC to a selection signal input terminal CE of a memory block M2, also an output terminal 5 of the decoder DEC to an input terminal CE of a memory block M3. Therefore, if several kinds of memory assignments are set, and if output terminals of the decoder DEC are connected to selection signal input terminals CEs of the memory blocks M1-M3 through a switching circuit SW so that they can be switched, a memory assignment can be realized with a simple switching operation.
申请公布号 JPS58205971(A) 申请公布日期 1983.12.01
申请号 JP19820087931 申请日期 1982.05.26
申请人 HITACHI SEISAKUSHO KK 发明人 HARA SHIYUUICHI
分类号 G06F12/06;G11C8/12 主分类号 G06F12/06
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