发明名称 GENERATOR OF MEMORY ADDRESS INFORMATION SIGNAL
摘要 PURPOSE:To use a memory efficiently, by providing three numeral information signal generating circuits and numeral error information signal generating circuits so as to generate write and readout addresses and detecting underflow and overflow. CONSTITUTION:A readout data number signal from each of signal selecting circuits 9, 12 and an output of an absolute address generator 14 are outputted selectively, then numerals represented with the output of a relative address generator 8 and that of the generator 14 are summed and a signal corresponding to the readout address obtained from the summation is outputted from a full- adder 11. When a write data number signal from each of the circuits 9, 12 and an output of an absolute address generator 13 are outputted selectively, a signal corresponding to a write address obtained by summing numerals represented by the output of the generator 8 and the output of the generator 13 is outputted from the adder 11. Further, the overflow and/or underflow is detected by obtaining the difference between numerals represented with the output of the generators 13 and 14.
申请公布号 JPS58205908(A) 申请公布日期 1983.12.01
申请号 JP19820090222 申请日期 1982.05.27
申请人 PIONEER KK 发明人 OKA MORIHISA
分类号 G11B3/00;G11B7/00;G11B7/004;G11B20/10;G11B20/12 主分类号 G11B3/00
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