| 摘要 |
PURPOSE:To reduce the number of signal lines and the load on a bus controller while keeping high-speed control operation and the simplicity of hardware, by allotting use of a common bus on specific priority basis for the numbers of devices with master functions. CONSTITUTION:An optional master device in an optional group, when it enters a bus use request state, sends a bus use request signal A to a bus use request line common in the group to which the master device belongs, in synchronization with a clock signal CLK fed from a clock signal line 2, and also outputs a use inhibiting signal to an intergroup bus use permission line. Once detecting that the common bus is usable, a bus controller 1 scans bus use request lines 31, 32-3n and permits a master device group with top priority corresponding to a bus use request line on which the bus use request signal is present to use the bus. |
