| 摘要 |
PURPOSE:To facilitate the control over DMA and to remove the restriction on the processing time of a CPU, by allotting intermemory block transfer based on DMAC to the former half of each machine cycle of the CPU, i.e. internal processing time of the CPU. CONSTITUTION:When even one group of indication data are set in buffers 24- 26, the indication data are transferred to counters 21-23 and a control circuit 29 starts DMA operation. Data is read out of an area of a memory 3 with an address indicated by a transfer origin address counter 21 and stored in a data buffer 28. Then, the data of the data buffer 28 is written in an area of the memory 3 with an address shown by a transfer destination address counter 22. At the same time, the value of a counter 23 for the number of transfer words is decreased by one on every DMA operation. When the value of the counter 23 is reduced to 0, one-block DMA operation is completed. |
