| 摘要 |
PURPOSE:To discriminate a ternary state with an input terminal, by supplying both pull-up and pull-down voltages to a signal line with different clocks and then storing and holding the level of said signal line. CONSTITUTION:Latches L1 and L2 latch ''0'' with a signal line DT kept at L level even though clocks phi1 and phi2 are turned on since a resistance RP is sufficiently smaller than resistances R1 and R2 in case IN is set at L level. When the IN is set at H level, the line DT is kept at H level although clocks phi1 and phi2 are turned on. Then the latches L1 and L2 latch ''1''. When the IN is open, the line DT is pulled down to L level by the R2 with ON of the clock phi1. Thus the latch L1 latches ''0'', and the DT is pulled up to H level by the R1 when the clock phi2 is turned on. Therefore, the latch L2 latches ''1''. |
