发明名称 STORAGE DEVICE
摘要 <p>PURPOSE:To improve the operating speed and to decrease the memory capacity, by providing a gate circuit for each ROM and reading out the same memory content through plural address lines at the same time. CONSTITUTION:An output of decoders 5, 6 applied with two groups of addresses AA0-AAn and AB0-ABn respectively access ROM element groups (A0-Aa)1 and (B0-Ba)2 via respective address lines and OR circuits 3, 4. Simultaneously, an output of the decoders 5, 6 controls gate circuit groups (A'0-A'a)11 and (B'0-B'a)12 of the groups 1, 2 respectively, and a readout output line is corresponded with the address line. Thus, the content of the same ROM is read out on the plural address lines at the same time, the capacity is reduced and the readout processing speed is improved.</p>
申请公布号 JPS58200495(A) 申请公布日期 1983.11.22
申请号 JP19820083800 申请日期 1982.05.18
申请人 KAWAI GATSUKI SEISAKUSHO:KK 发明人 MISHIMA TOSHIO
分类号 G11C17/00;G06F12/06;G11C7/00;G11C8/00;G11C8/12 主分类号 G11C17/00
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