发明名称 PHASE LOCKED LOOP
摘要 PROBLEM TO BE SOLVED: To provide a phase locked loop that is configured to be in operation according to a plurality of characteristics flexibly with high reliability over a sufficiently wide frequency range. SOLUTION: The phase locked loop includes an input comparator 2 that generates a deviation signal, and the deviation signal is used to drive an oscillator 5 to generate an output signal (CLKOUT) locked to an input signal. The oscillator 5 is operated according to a plurality of characteristics under the control of a control means 8 including a search means. The search means executes a 1st search stage for a characteristic group where an operation of the oscillator 5 is allowed by scanning the range that can gradually be reduced according to a general binary search procedure. When the 1st search step is finished, other fine search means identifies an optimum operating point to automatically compensate the fluctuation that may be possible.
申请公布号 JP2000183734(A) 申请公布日期 2000.06.30
申请号 JP19990350304 申请日期 1999.12.09
申请人 CSELT SPA (CENT STUD E LAB TELECOMUN) 发明人 BALISTRERI EMANUELE;BURZIO MARCO
分类号 H03L7/099;H03L7/10;H03L7/107 主分类号 H03L7/099
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