发明名称 MASTER SLICE LSI
摘要 PURPOSE:To reduce the number of pieces of no wiring of automated wirings at the center part of a chip by a method wherein no cell arranged regions are provided on the lines of circuit elements at the center part of the chip, and wirings to connect between cells are provided thereto crossing at a right angle to the lines of the circuit elements. CONSTITUTION:The desired cells 3 are arranged on the chip 1, and the cells 3 thereof are connected with straight lines 9. At this time, when the places to make the straight lines 9 thereof to cut the cells 3 vertically are made as the no cell arranged regions, arrangement of the vertically directional wirings 6 to connect between the cells 3 is facilitated. Nevertheless, when the places to make the straight lines 9 to cut vertically the cells 3 are made totally as the no cell arranged regions, because it causes insufficiency of the number of the cells, rough distribution of the straight lines 9 is investigated to find out the places A to be concentrated especially with the straight lines 9. Then the places A thereof are used as the no cell arranged regions 8 to improve arrangement of the cells 3. Accordingly, by providing the no cell arranged regions at the center part of the cells to be used as the vertically directionally wiring regions, the vertically directionally wiring regions at the center part of the chip are ensured, and the no wiring regions at automatically assembling time of the master slice LSI having the logically mounting ratio of less than 100% are reduced to the minimum.
申请公布号 JPS58197747(A) 申请公布日期 1983.11.17
申请号 JP19820079921 申请日期 1982.05.14
申请人 HITACHI SEISAKUSHO KK 发明人 CHIBA KIYOUJI;TAKEUCHI HISAHIRO
分类号 H01L21/82;H01L27/118;(IPC1-7):01L21/82 主分类号 H01L21/82
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