Data processing system with system bus for transfer of information.

摘要

A CPU (10) communicates with various devices on a system bus (11) and communicates with two further groups of devices by way of interfaces (14) and (14A) and corresponding buses (15) and (15A) whose timing and control characteristics are different from each other and from those of the system bus (11). The interface (14) polls the devices which may be on its bus (15) and keeps a record of the devices actually present. When access to a device is required, the interface (14) provides access via its bus (15) if the device is recorded as present on that bus. Otherwise it provides a signal to the interface (14A) to enable access via the corresponding bus (15A). The bus (11) operates with a two-phase cycle and a device requesting access to the bus does so in the first phase of a cycle and asserts a signal preventing other devices putting data on the bus. A device putting data on the bus in the second phase asserts a signal locking out other devices and a further signal keeps the bus locked if the time taken for the data transfer is such as to extend into the next operating cycle.