| 摘要 |
PROBLEM TO BE SOLVED: To provide an address buffer circuit which do not retain any mistaken address signal, even if the timing of address signal Ai is changed. SOLUTION: If the complementary address signals Xi, /Xi are retained on the two FF(Flip Flop) 24 and 25 of the address latch part 20A, the entrapment permission signal EN becomes 'L', the outputs of NAND 21A, 23A become 'H'. Thereby the retained contents of FF 24, 25 do not change. When the FF 24, 25 are reset by clearance signal CL, the entrapment permission signal becomes 'H'. In such a way the address signal Ai read from synchronized part 10 by synchronizing with clock signal CK is retained in FF 24 and 25 according to the timing of address entrapment permission signal EN.
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